Web Reference: External debug refers to debug software running somewhere else, debugging the RISC-V platform via a debug transport like JTAG. The entire document provides features that are useful for external debug. Using SmartDebug, you can debug Microchip FPGA arrays and SerDes via their respective Joint Test Action Group (JTAG) port(s) without requiring an internal logic analyzer. SmartDebug can also capture FPGA device status, MSS register access, and flash and DDR memory content. If you are an SoC designer, this guide helps you design debug and trace infrastructure using Arm CoreSight IP products such as the CoreSight SoC components. It gives a high-level view of the goals when designing CoreSight debug infrastructure. Before you begin
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